MSP8120 pmc-2070368, issue 1 ? copyright pmc-sierra, inc. 2007 all rights reserved. proprietary and confidential to pmc-sierra, inc. and for it s customers? internal use. multi-service security processor product overview pmc-sierra's MSP8120 multi-service security-enabled processor is designed to meet the needs of netw orking, security appliances, and network attached st orage applications. the MSP8120 integrates standards-ba sed security hardware to accel- erate internet protocol security (i psec) and secure socket layer (ssl) performance for security applia nces, firewalls, networking, and storage applications. the MSP8120 is part of the msp8100 series of highly-integrated, feature-rich products that incorp orate the high performance, power- efficient mips 34k core. the proce ssor provides pci, dual ethernet, rom, flash, ddr, and low-speed peripheral interfaces, which are connected internally to the mips 34k core by a high-bandwidth multi- service bus. product highlights integrated security subsystem ? integrated security subsystem: ? dedicated 2-channel dma controller for security packet processing ? ipsec engine: ? supports all ipsec packet transfor ms and implements ssl packet transforms ? implements des/3des/aes cr ypto and sha-1/md-5 hash algorithm support ? integrated queue manager fo r intelligent buffer management ? random number generator mips 34k microprocessor core ? supports mips32 release 2 instruction set ? 400 mhz operation ? 9-stage pipeline ? 64 kbyte instruction and data caches ? mips16e code compression ? 32-bit address paths, 64-bit data paths to caches and external interface ? dsp instruction set extensions ? ejtag debug and off-chip trace support programmable memory management unit ? 8-entry instruction tlb (i tlb) and data tlb (dtlb) ? 32 dual-entry joint tlb (jtlb) ? jtlbs are sharable under software control usb 2.0 controller and phy ? both host and device mode of operation ? supports low-speed (ls) operation (1.5 mbit/s), full-speed (fs) operation (12 mbit/s) and hi-speed (hs) operation (480 mbit/s) system interrupt controller ? handles interrupts for on-chip peripherals and 8 external interrupts ? supports up to 32 pci message signaled interrupts (msi) released product brief unprotected network MSP8120 ethernet switch ? ? ? protected lan clients ? ? ? rmii rmii MSP8120 network security application benefits ? high-performance 400 mhz mips 32 core enables demanding packet processing and netw ork security applications ? highly integrated syst em-on-a-chip (soc) solution simplifies board design, reducing component and overall system cost ? hardware ipsec processing frees up the cpu for other applications ? optimized memory controller provides low latency, high bandwith access to sdram (333 mhz ddr-2)
MSP8120 multi-service security processor corporate head office: pmc-sierra, inc. mission towers one 3975 freedom circle santa clara, ca, 95054, u.s.a. tel: 1.408.239.8000 fax: 1.408. 492.1157 pmc-2070368, issue 1, ? copyri ght pmc-sierra, inc. 2007. all rights reserved. for a complete list of pmc-sierra?s trademarks , visit www.pmc-sierra.com/legal/. other product and company names mentioned herein may be the trademarks of their respective owners. for corporate information, send email to: info@pmc-sierra.com. all product documentation is available on our web site at: www.pmc-sierra.com. operations head office: pmc-sierra, inc. 100-2700 production way burnaby, bc v5a 4x1 canada tel: 1.604.415.6000 fax: 1.604.415.6200 high performance multi-service bus (ms bus) architecture ? 32 bits at 166 mhz (5.33 gbit/s) ? dma engines integrated for the ethernet macs, usb, tdm interface, security engine, and block copy engine system logic and peripherals module ? 3.3 v pci local bus 2.3-compliant host interface ? configurable external local bu s interface that supports data transfers up to 25 mbytes per second ? glueless interface to x8 flash memories ? clock manager and boot controller ? serial peripheral interface/ microprocessor peripheral interface (spi/mpi) ? two-wire serial interface ? 20 gpio pins ? system interrupt controller (int ernal and external interrupts) ? two external timers / clock generator ? two universal asynchronous serial (uart) interfaces clock manager and boot controller ? in single crystal mode, all on-chip cl ocks are generated from a single 36 mhz crystal ethernet interface ? two independent 10/100 et hernet mac controllers ? user selectable media-independent interface (mii) or rmii (reduced mii) interface on each mac applications ? security appliances ? firewalls ? networking applications ? storage applications block diagram fifo 4-way data router bus arbiter clock manager slp control interface dxu system logic and peripherals pci pci control reg bcp elb uart0 uart1 spi twi gpio timer ddr sdram controller memory control interface dxu cpu interface cic mips 34k core fifo dxu jtag dft multi-service bus xtal (r)mii (r)mii irq ejtag ipsec dxu dxu mab usb dxu bridge dma mac dxu bridge dma mac
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